/***************************************************************************//**
* \file CapSense_Adc_INT.c
* \version 3.0
*
* \brief
*   This file contains the source code for implementation of the CapSense 
*   component ADC functionality Interrupt Service Routine (ISR).
*
* \see CapSense P4 v3.0 Datasheet
* 
*//*****************************************************************************
* Copyright (2016), Cypress Semiconductor Corporation.
********************************************************************************
* This software is owned by Cypress Semiconductor Corporation (Cypress) and is
* protected by and subject to worldwide patent protection (United States and
* foreign), United States copyright laws and international treaty provisions.
* Cypress hereby grants to licensee a personal, non-exclusive, non-transferable
* license to copy, use, modify, create derivative works of, and compile the
* Cypress Source Code and derivative works for the sole purpose of creating
* custom software in support of licensee product to be used only in conjunction
* with a Cypress integrated circuit as specified in the applicable agreement.
* Any reproduction, modification, translation, compilation, or representation of
* this software except as specified above is prohibited without the express
* written permission of Cypress.
*
* Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH
* REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
* Cypress reserves the right to make changes without further notice to the
* materials described herein. Cypress does not assume any liability arising out
* of the application or use of any product or circuit described herein. Cypress
* does not authorize its products for use as critical components in life-support
* systems where a malfunction or failure may reasonably be expected to result in
* significant injury to the user. The inclusion of Cypress' product in a life-
* support systems application implies that the manufacturer assumes all risk of
* such use and in doing so indemnifies Cypress against all charges. Use may be
* limited by and subject to the applicable Cypress software license agreement.
*******************************************************************************/
#include "cytypes.h"
#include "cyfitter.h"
#include "CapSense_Adc.h"
extern uint16 CapSense_AdcVref_mV;


/**
* \if SECTION_ADC_INTERRUPT
* \addtogroup group_capsense_interrupt
* \{
*/

#if (CapSense_ADC_EN)    
    
/*******************************************************************************
* Function Name: CapSense_AdcIntrHandler
****************************************************************************//**
*
* \brief
*   This is an internal ISR function for ADC implementation.
*
* \details
*   This ISR is triggered after a measurement completes or during calibration
*   phases.
*   
*   To use the entry or exit callbacks, define
*   CapSense_ADC_[ENTRY|EXIT]_CALLBACK
*   and define the corresponding function, CapSense_Adc[Entry|Exit]Callback().
*
*
*******************************************************************************/
CY_ISR(CapSense_AdcIntrHandler)
{
    static uint16 tVssa2Vref;
    static uint16 tVdda2Vref;
    
    #ifdef CapSense_ADC_ENTRY_CALLBACK
        CapSense_AdcEntryCallback();
    #endif /* CapSense_ADC_ENTRY_CALLBACK */

    /* Un-request the interrupt. */
    CY_SET_REG32(CapSense_AdcINTR_PTR, CapSense_AdcINTERRUPT_SET);
    CY_SET_REG32(CapSense_AdcINTR_MASK_PTR, CapSense_AdcINTERRUPT_CLEAR);
    
    /* ADC could have been converting or calibrating; handle each differently. */
    if (CapSense_AdcSTATUS_CONVERTING == (CapSense_dsRam.adcStatus \
        & CapSense_AdcSTATUS_FSM_MASK))
    {
        uint32 tmpResult;
        uint8 tmpChId = CapSense_dsRam.adcStatus \
            & (uint8)(CapSense_AdcSTATUS_LASTCHAN_MASK);
        
        tmpResult = CY_GET_REG32(CapSense_AdcADC_RES_PTR);
                
        /* HSCMP polarity will have been 0 if sourcing.  Apply 'sink' conversion. */
        if(0UL != (tmpResult & CapSense_AdcADC_RES_HSCMPPOL_MASK))
        {
            tmpResult = CapSense_AdcVref_mV - \
                (((tmpResult & CapSense_AdcADC_RES_VALUE_MASK) * \
                CapSense_AdcVref_mV) / tVssa2Vref);
            /* Depending on noise, signals close to 0 mV can cause underflow. Clip them to 0. */
            if (tmpResult > CapSense_AdcUNDERFLOW_LIMIT) {tmpResult = 0U;}
        }
        else
        {
            tmpResult = CapSense_AdcVref_mV + \
            (((tmpResult & CapSense_AdcADC_RES_VALUE_MASK) * \
              ((uint32)CapSense_CYDEV_VDDA_MV - (uint32)CapSense_AdcVref_mV)) / tVdda2Vref);
        }
        CapSense_dsRam.adcResult[tmpChId] = (uint16)(tmpResult);
        CapSense_SetAdcChannel(tmpChId, CapSense_AdcCHAN_DISCONNECT);
        CapSense_dsRam.adcStatus = CapSense_AdcSTATUS_IDLE;
    }
    else if (CapSense_AdcSTATUS_CALIBPH1 == (CapSense_dsRam.adcStatus \
        & CapSense_AdcSTATUS_FSM_MASK))
    {
        tVssa2Vref = (uint16)(CY_GET_REG32(CapSense_AdcADC_RES_PTR) \
        & CapSense_AdcADC_RES_VALUE_MASK);
        CapSense_dsRam.adcStatus = CapSense_AdcSTATUS_CALIBPH2;
        CY_SET_REG32(CapSense_AdcINTR_MASK_PTR, \
            CapSense_AdcINTERRUPT_SET);
        CapSense_StartAdcFSM(CapSense_AdcMEASMODE_VREFBY2);
    }
    else if (CapSense_AdcSTATUS_CALIBPH2 == (CapSense_dsRam.adcStatus \
        & CapSense_AdcSTATUS_FSM_MASK))
    {
        /* Disconnect amuxbusB, Connect VDDA to csdbusB */
        CY_SET_REG32(CapSense_AdcSW_BYP_SEL_PTR, 0UL);
        CY_SET_REG32(CapSense_AdcSW_SHIELD_SEL_PTR, \
            CapSense_AdcSW_SHIELD_VDDA2CSDBUSB);
        
        CapSense_dsRam.adcStatus = CapSense_AdcSTATUS_CALIBPH3;
        CY_SET_REG32(CapSense_AdcINTR_MASK_PTR, CapSense_AdcINTERRUPT_SET);
        CapSense_StartAdcFSM(CapSense_AdcMEASMODE_VIN);
        
    }
    else if (CapSense_AdcSTATUS_CALIBPH3 == (CapSense_dsRam.adcStatus \
        & CapSense_AdcSTATUS_FSM_MASK))
    {
        /* Reconnect amuxbusB, disconnect VDDA */
        CY_SET_REG32(CapSense_AdcSW_SHIELD_SEL_PTR,
            CapSense_AdcSW_SHIELD_DEFAULT);
        CY_SET_REG32(CapSense_AdcSW_BYP_SEL_PTR, 
            CapSense_AdcSW_BYP_DEFAULT);
                
        CapSense_dsRam.adcStatus = CapSense_AdcSTATUS_IDLE;
        
        tVdda2Vref = (uint16)(CY_GET_REG32(CapSense_AdcADC_RES_PTR) \
        & CapSense_AdcADC_RES_VALUE_MASK);
    }
    /* If interrupt is called without defined ADC state, do nothing. */
    else{}
    
    #ifdef CapSense_ADC_EXIT_CALLBACK
        CapSense_AdcExitCallback();
    #endif /* CapSense_ADC_EXIT_CALLBACK */
}


#endif /* CapSense_ADC_EN */

/** \}
 * \endif */

 
/* [] END OF FILE */
